Japanese Patent Application Laid-Open No. 2010-538358 (Patent Document 1), Japanese Patent Application Laid-Open No. 2013-138177 (Patent Document 2), Japanese Patent Application Laid-Open No. 2014-11169 (Patent Document 3), U.S. Pat. No. 8,653,676 (Patent Document 4), and Japanese Patent Application Laid-Open No. 2014-11284 (Patent Document 5) describe semiconductor devices in which a plurality of semiconductor chips are electrically connected to each other via an interposer.